Pipelining
Computer Science: OCR A Level, topic 1.1.6
Pipelining
Pipelining is a feature which allows more processor operations to take place in less time.
Idle processor
- Processors typically complete one instruction before moving on to the next.
- This means parts of the processor are idle while the instruction is completed.
- This is an inefficient process.
Effect of pipelining
- Pipelines ensure as much of the processor is in use all at one time and increase efficiency of the computer system.
- Pipelining is usually split into two pipelines:
- Instruction Pipeline.
- Arithmetic Pipeline.
Instruction pipeline
- The instruction pipeline will pre-fetch the next instruction and data and store it in a register.
- As one instruction leaves the current instruction register (CIR), the next one is ready to be loaded and decoded.
- At any given point, there are instructions being fetched, decoded and executed.
Arithmetic pipeline
- The arithmetic pipeline divides up an arithmetic operation into its individual steps.
- Each step is performed overlapping the next step.
Pipelining
Pipelining speeds up the CPU. It overlaps the fetch, decode and execute stages for several instructions at once.
What is pipelining?
- Pipelining is a technique that speeds up the CPU.
- It overlaps the stages of the fetch-decode-execute cycle.
- This lets the CPU work on several instructions at once.
- Without pipelining, the CPU finishes one whole instruction before it starts the next.
How pipelining works
- The CPU splits each instruction into stages, usually fetch, decode and execute.
- Each stage is handled by a different part of the CPU.
- This means several instructions can move through the pipeline at the same time.
- While one instruction executes, the next can be decoded and a third can be fetched.
- This is similar to a factory line, where each worker completes one stage of a product.
Benefits of pipelining
- Pipelining increases the CPU's throughput.
- Throughput - the number of instructions processed per second.
- More instructions are completed in the same amount of time.
- It makes better use of CPU resources, because different parts of the CPU work on different instructions at once.
- This improves performance without needing a faster clock speed.
Pipeline hazards
- A pipeline hazard is a problem that stops the next instruction running in its planned clock cycle.
- A data hazard happens when an instruction needs a result from a previous instruction that is not ready yet.
- A control hazard happens when a branch instruction means the CPU does not know which instruction to fetch next.
- When a hazard occurs, the CPU may need to stall the pipeline, which reduces the performance gain.